VHDL的優(yōu)化與檢測
摘要:在電子技術設計領域，可編程邏輯器件（PLD）的應用，已有了很好的普及性。這些器件為數字系統的設計帶來極大的靈活性。由于該器件可以通過軟件編程而對其硬件的結構和工作方式進行重構，使得硬件的設計如同軟件設計那樣方便快捷。這一切極大地改變了傳統的數字系統設計方法，設計過程甚至設計觀念。從應用的廣度和深度來說，由于電子信息領域的全面數字化，基于EDA的數字系統的設計技術具有更大的應用市場和更緊迫的需求性。
EDA要求用硬件描述語言, （HDL）來描述硬件電路的了行為和功能。作為IEEE的標準語言，VHDL在范圍內*國家的電子系統設計領域獲得廣泛應用。本論文就是通過VHDL的各種優(yōu)化設計，仿真，VHDL的實現來介紹VHDL的基本概念，特點，應用及優(yōu)化過程。
關鍵詞:VHDL；優(yōu)化；歧義文法；

VHDL Optimization and Examination
Abstract:In technology electron field, the using of programme,logic device is getted good gain ground. Those parts of an apparatus bring huge agility for digit systems design Because these device can compose the structure and working of the hardware again by software programme, it make the design of hardware as convenient as the design of software.The whole shoot change maximumly the design way.design process,even design ideas of the conventional digit system,Saying flom the extent and depth of the applying,the design technology of digit system base on EDA take on more application market and more pressing demand.
EDA describing hardware circuits action and function HDL. As a standard language of IEEE, VHDL win abroad application in electron system design field of advance country in the seven seas. This paper introduced the basic concept, characters and appliance process of the VHDL by designing, simulating, and VHDL realization of all kinds of VHDL optimization
KEY WORDS:VHDL；optimization；grammar；examination